Efficient implementation for BFV fully homomorphic encryption algorithm based on Zynq platform

Abstract

An efficient implementation scheme for the BFV fully homomorphic encryption algorithm was proposed on the Zynq platform. This scheme effectively integrated the negative wrapped convolution with the number theoretic transform (NTT) algorithm, optimizing and accelerating the polynomial multiplication process. Furthermore, it adopted a pipeline design and parallel hardware architecture to enhance the RNS implementation of the BFV algorithm. The system efficiently implemented data transmission between the ARM processor and FPGA using the AXI-DMA transfer mechanism. Test results on the Zynq UltraScale+MPSoC ZCU102 platform show that the system performs a homomorphic addition in just 0.024 ms and a homomorphic multiplication in 5.779 ms at a 200 MHz clock frequency, which includes 0.874 ms for ciphertext transmission. Compared to the implementations of the SEAL and OpenFHE libraries, the proposed scheme achieves efficiency improvements of 4.63 and 6.79 times for homomorphic addition, and 4.43 and 2.95 times for homomorphic multiplication, providing an important reference for the practical engineering implementation of fully homomorphic encryption algorithms.

Keywords

• fully homomorphic encryption;BFV algorithm;residual number system;number theoretic transform;hardware implementation