WL-WD: Wear-Leveling Solution to Mitigate Write Disturbance Errors for Phase-Change Memory

Abstract

Phase-change memory (PCM) is a promising non-volatile memory device due to its attractive properties such as fast access time and byte-addressability. However, PCM is still difficult to be used as a main memory because of its weakness in endurance and write disturbance. Conventional wear-leveling algorithms have attempted to handle short endurance, but they have not addressed the issue of write disturbance even though both issues are caused by write operations to PCM. This paper proposes a wear-leveling algorithm that addresses not only the endurance, but also the write disturbance. From the observation that the write disturbance errors and short endurance issues mostly take place in hot addresses, the proposed algorithm first detects hot addresses and maps them to ‘hot’ regions, which are customized memory regions designed to be robust to write disturbance errors and to support effective wear-leveling. The ‘hot’ region is not fixed to a specific part, but it moves over an entire memory space to make every cell belong to ‘hot’ regions in a uniform manner. On the other hand, cold addresses are mapped in ‘normal’ memory regions by simple linear mapping to reduce the hardware overhead. The proposed algorithm can reduce the write disturbance errors by more than 70% with only a slight instruction per cycle (IPC) degradation. Moreover, the wear-leveling performance is also enhanced by more than 3% compared to other wear-leveling algorithms.

Keywords

• Phase-change memory
• write disturbance error
• wear-leveling
• memory reliability
• memory endurance