IEEE Access (Jan 2024)

Capacitor-Free Scalable CMOS Neuron Circuit With Compact Design and Low Power Consumption

  • Zixuan Rong,
  • Prabal Bhatnagar,
  • J. Joshua Yang,
  • Yong Chen

DOI
https://doi.org/10.1109/ACCESS.2024.3485025
Journal volume & issue
Vol. 12
pp. 158258 – 158265

Abstract

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We present a capacitor-free, scalable CMOS neuron circuit that offers significant benefits, including a compact circuit area, low power consumption, adjustable firing threshold, and scalability. This circuit generates output pulses with widths that increase in proportion to the input current magnitude. It also features an adjustable firing threshold (1-6 nA), indicating the minimum input current required to trigger an output pulse. Fabricated using standard 180 nm CMOS technology, the circuit occupies an area of $200~{\mu }$ m2 and consumes 1.4 pJ of energy per output pulse.

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