Experimental and numerical studies on the power RF N-LDMOS transistor under cold and hot thermal shock tests based aging mechanism

Abstract

This paper describes a new methodology to initiate a thermal accelerated aging test, and identify the key parameters affecting the reliability of a power RF N-LDMOS transistor. The method is based on two aging techniques namely cold and hot thermal shock tests (TST, air-air test), carried out at different junction temperatures varying from −25 °C to +75 °C as well as a deep theoretical analysis. We particularly focus on the thermal chock degradation of three important bond parameters: time, temperature and channel current. The experimental results show that the degradation phenomenon at cold TST is more important than at hot TST. Moreover, we observe an increase in the amplitude of the leakage gate current IGS as well as a shift in the following electric parameters: threshold voltage VTH, transconductance GM, on-state resistance RDSON, feedback capacity CRSS, and S parameters. 3D Silvaco-ATLAS based physical simulations are also carried out, and reveal the effect of the TST on the degradation of the structure zone, which in turn has led to the shift in the values of the electrical parameters. A deep theoretical analysis confirms the observed phenomenon, and shows that the degradation process leads to an increased carrier injection into the developed silicon dioxide layer (SiO2) and/or into the interface state Si/SiO2. Therefore, much more interface states are created due to a located maximum impact ionization rate at the gate.

Keywords

• Thermal shock test
• Hot carrier
• Power RF LDMOS
• Temperature effects
• Failure analysis