A 65-nm CMOS 1 GS/s 45 mW Hybrid Digital-to-Analog Converter (DAC) With Digital Deglitch Mechanism Achieving 13.83 fJ/step FOM for 5G New Radio Sub-6 GHz Applications

Abstract

This paper presents a high speed 16-bit hybrid Digital-to-Analog converter (DAC) featuring an innovative digital filtering mechanism designed to eliminate glitches and ensure high signal integrity at an operational speed of 1 GS/s. Fabricated using a 65 nm process and operating on a 1 V supply, the hybrid DAC integrates a current-steering architecture for the six most significant bits (MSB) and a binary-weighted resistive ladder for the ten least significant bits (LSB), effectively managing power consumption. Occupying an active area of 0.06 mm2, the DAC consumes 45 mW of power. It demonstrates differential nonlinearity (DNL) ranging from −0.27 to +0.25 LSB and integral nonlinearity (INL) from −0.33 to +0.34 LSB. Performance metrics at the Nyquist frequency include a spurious-free dynamic range (SFDR) of 72 dB and a signal-to-noise-and-distortion ratio (SNDR) of 70 dB, yielding a figure of merit (FOM) of 13.83 fJ/step. The DAC demonstrates resilience to process, voltage, and temperature (PVT) variations, with a deviation of less than 4%, confirming its reliability for the 5G New Radio (NR) sub-6 GHz application. The proposed hybrid DAC provides a fast, accurate, and power-efficient solution for high-speed, high-resolution data conversion catering to the demanding requirements of 5G NR sub-6 GHz systems.

Keywords

• CMOS
• digital-to-analog converter (DAC)
• current-steering
• resistive ladder
• signal-tonoise-distortion ratio (SNDR)
• 5G new radio (NR)