Area-Efficient digital filtering based on truncated multiply-accumulate units in residue number system 2n-1,2n,2n+1

Abstract

High resource consumption of digital filtering devices is one of the main practical problems of digital signal processing. Parallel data processing is one of the most effective approaches to improve the quantitative characteristics of such devices. This paper proposes a method for filtering signals using Truncated Multiply-and-Accumulate units (TMAC) in the residue number system (RNS) using moduli of a special type 2n-1,2n,2n+1. These moduli reduced hardware costs and power consumption compared to state-of-the-art approaches for a 32-bit RNS filter by up to 23% and up to 22.3%, respectively, with a delay increase of 131%. The proposed approach allowed to reduce the device area by up to 14% with comparable energy expended for a 48-bit RNS filter, but the device delay increased by 81%. The results obtained open up the possibility of creating area-efficient and power-efficient devices.

Keywords

• Digital signal processing
• FIR filter
• Moduli of a special type
• Unit-gate model
• Diminished-one technique
• Low-power devices