Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices

Abstract

This paper presents the behavioral modeling of three circuit architectures, which are suitable for heartbeat detection in wireless healthcare applications. The developed front-end models implement an analog system that detects the heartbeats for lower power consumption and higher detection accuracy without digital signal processing. Therefore, the circuit blocks and their critical specifications specifically regarding the noise and bandwidth are evaluated. The architectures are implemented in Verilog-A and their behavior simulations use real electrocardiogram (ECG) signals with different characteristics and conditions. All architectures have amplification, band-pass and notch response blocks as their first three stages. Then, the first circuit architecture detects the heartbeat using an adaptive threshold based on a pulse width approach. The second heartbeat detection scheme finds the maximum and minimum values of each beat using a sample-and-hold-based peak detector. The third model uses a similar peak detection scheme, but delays the analog signal for better precision. The simulation results show that all models can detect heartbeats when the input noise is less than $20 \mu V$ , the third having the highest noise tolerance of around $50 \mu V$ . For the ECG signal to maintain its characteristics with respect to its positive and negative peak, the bandpass response should present a low cutoff frequency below 10 Hz.

Keywords

• Analog front-end
• behavioral modeling
• healthcare
• heartbeat detection
• verilog-A