Mathematical models and simulations of phase noise in phase-locked loops

Abstract

Phase noises in Phase-Locked Loops (PLLs) are a key parameter for communication systems that contribute the bit-rate-error of communication systems and cause synchronization problems. Accurate predictions of phase noises through mathematical models are consequently desirable for practical designs of PLLs. Despite many phase noise models derived from noise sources from electronic devices such as an oscillator and a multiplier have been proposed, no phase noise models that include noises from loop filters have specifically been investigated. This paper therefore investigates the roles of loop filters in phase noise contribution. The major scopes of this paper is a detailed analysis and simulations of phase noise models resulting from all components. i.e. a voltage-controlled oscillator, a multiplier and a filter. Two particular second-order passive and active low-pass filters are compared. The results show that simulations of phase noises without an inclusion of filter noises may not be accurate because the filter noises, particularly the active filter, significantly contribute the total phase noise. Moreover, the passive filter does not significantly dominate the phase noise at low offset frequency while the active filters entirely dominate. Therefore, the passive filter is a more efficient filter for PLL circuit at low offset frequency. The phase noise models presented in this paper are relatively simple and can be used for accurate phase noise prediction for PLL designs.

Keywords

• phase-locked-loop
• phase noise
• voltage control oscillator
• phase detector
• loop filter
• main divider