Low Insertion Loss and Non-Blocking Microring-Based Optical Router for 3D Optical Network-on-Chip

Abstract

With the advent of complex computing applications such as cloud computing and artificial intelligence, the utilization of multicore processors has become one of the best solutions to improve the computation performance. Benefitted from the technologies of silicon-photonic-based communication and three-dimensional (3-D) integration, the 3-D optical network-on-chip (3-D ONoC) has attained extensive attentions as a new multicore architecture, providing high communication bandwidth, as well as low transmission delay and power consumption. As the main part of 3-D ONoCs, the structures of topology and optical router (OR) heavily affect the transmission efficiency of the whole network. In this paper, we propose a mesh-based topology and a novel cost-efficient 6 × 6 nonblocking OR structure. Different from the traditional 3-D ONoC topology that needs seven-port ORs to realize the data transmission, the OR mentioned in our solutions only consumes six ports. This improvement effectively reduces the number of optical switching elements and cross waveguides in ORs, lowering the power consumption and hardware costs of the system. The simulation analysis based on the modified Noxim simulator demonstrates that our method performs well in terms of mitigating the OR- and network-level insertion loss, shrinking the floorplan/chip area and improving the network scalability over benchmarks.

Keywords

• Multi-core platform
• 3D ONoC
• cost efficiency
• non-blocking optical router