Design and implementation of SRIO multiple channel control system based on FPGA

Abstract

In board and chip interconnection, SRIO(Serail RapidIO) has higher bandwidth and reliability than other protocol. In this paper, the HELLO format of the MSG (message) interface is used to multi-interface design method at the sending end, and the Round-Robin processing mechanism is used internally to realize the competition processing of the multi-channel interface sharing one SRIO interface when sending data at the same time. It supports the arbitrary expansion of the number of interfaces and the clock domain. After testing and verification, the system can realize the data sending and receiving of 64 channels under different clocks at most, and the delay between the single channel and the packet can be as low as 4μs. It has good application value in the direction of SRIO transmission application.

Keywords

• xilinx
• srio
• multiple-channel
• round-robin