Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

Abstract

This study presents an accurate model for non-monotonic layout-dependent effects (LDEs) measured using 10nm-class dynamic random access memory technology. To collect the LDE measurement data, a test module with an individually addressable array of 240 transistors has been developed. The proposed test module occupies a small area of 0.1 square millimeters with a density 15 times higher than that of typical scribe-line circuits. The proposed model employs a novel empirical function to precisely describe the non-monotonic dependence on each pair of geometrical parameters, such as the diffusion lengths, lateral/vertical spacings to the adjacent shallow trench isolations, and gate-to-contact distances. Additionally, this model can be easily realized as a sub-circuit model in standard circuit simulators, requiring only two additional tuning parameters for the core transistor. The fitted model demonstrates excellent agreement with the measured values obtained from test modules (802 transistors in total), achieving mean absolute errors of 0.7% for the drain current in the saturation region and 4.7 mV for the threshold voltage.

Keywords

• Addressable array circuit
• layout-dependent effects
• dynamic random-access memory
• scribe lines
• shallow trench isolation