Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime

Abstract

The p‐type nanowire field‐effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in‐depth technology computer‐aided design (TCAD) with quantum models for sub‐10‐nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence‐band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (Lg) by examining a set of primary DC and AC parameters. The cutoff frequency (fT) and maximum oscillation frequency (fmax) of the proposed device were determined to be 440.0 and 753.9 GHz when Lg is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe‐shell channel p‐type nanowire FET has demonstrated a strong potential for low‐power and high‐speed applications in 10‐nm‐and‐beyond complementary metal‐oxide‐semiconductor (CMOS) technology.

Keywords

• cmos technology
• high hole mobility
• low‐power high‐speed operation
• nanowire fet
• sige shell channel
• sub‐10‐nm logic technology
• valence‐band offset