Margin‐based reliability reinforcement method for stateful logic

Abstract

Abstract The memristive stateful logic can realize the memory and computation, thus effectively avoid the huge time and energy overhead caused by data moving between memory and computation units. However, the memristive stateful logic still faces the reliability challenges caused by the variability of memristor, which prevents it from practical applications. A reliability reinforcement method with low overhead in delay, area and peripheral circuits is thus needed to be studied urgently. This paper proposes a novel method of reliability reinforcement based on logic gates' margin. By optimizing circuit structure and driving voltage configuration, the margin of logic gates is improved to tolerant memristors' variability to the maximum extent, and thus reinforces logic gates' reliability. Simulations demonstrate that the proposed method can improve the allowed threshold variability range by 42% and 92% for 2‐input NAND gate and 2‐input OR gate, respectively. Benchmark with other methods shows that the proposed margin‐based reinforcement method achieves almost the same reliability reinforcement effect, but the overhead in area and peripheral circuit is greatly reduced.

Keywords

• memristor
• reliability
• stateful logic