An RF-SoC-Based Ultra-Wideband Chirp Synthesizer

Abstract

This paper presents the design and development of a digital two-channel chirp synthesizer using a field-programmable gate array (FPGA) device. To achieve an integrated solution, the design was implemented on radio-frequency system-on-chip (RF-SoC) technology that includes digital-to-analog converters (DACs) and other radio-frequency components on-chip. To overcome the timing errors in high-speed design with DACs operating at 6.144 GHz, a memory-stitching concept was used. A prototype was developed to validate this concept by generating a baseband chirp with a bandwidth of 1.7 GHz and a sweep time of 36 $\mu \text{s}$ . The synthetic chirp was upconverted to 3.572-5.272 GHz for use as the transmit signal for an ultra-wideband radar to characterize the chirp using a 1 km long optical delay line. The transmit signal was analyzed in terms of phase and amplitude errors and corrected for these errors. The root-mean-square (RMS) frequency deviation of the predistorted chirp from linearity over the 1.7 GHz bandwidth is 9.64 kHz, realizing a chirp linearity of 0.00057%. The measurement data show comparable performance of our chirp synthesizer against a commercially available arbitrary-waveform-generator (AWG) operating at a sampling rate of 60 GHz. The reported chirp synthesizer can be used in frequency-modulated continuous-wave (FM-CW) and stretch radars. Such radars are widely used for a variety of remote sensing measurements.

Keywords

• RF-SoC
• chirp-synthesizer
• FM-CW
• radar
• FPGA