Area and delay efficient RNS-based FIR filter design using fast multipliers

Abstract

In today's digital age, speed, and area are the primary design concerns. Increasing the rate at which multiplication and addition are performed has always been a need for developing cutting-edge technologies. Wallace multipliers, and Dadda multipliers, are one of the fastest multipliers used in many processors to accomplish fast arithmetic operations. A novel approach to design a LookUp Table (LUT) multiplier was proposed and implemented in Finite Impulse Response (FIR) filter. To improve the Residue Number System (RNS) based FIR filter's performance, several adders like Carry Look ahead (CLA) adder, Kogge Stone adder (KSA) and proposed adder architectures have been implemented. When compared with the 16 tap with 32 bit proposed adder with LUT multiplier, the hardware resource utilization (Logic Elements) is decreased by 5.97 % and in 32 tap with 16 bit combination, it decreases by 7.60 %.When compared with 32 tap with 4 bit word length, the proposed adder with LUT multiplier in the highlighted combinations, the Fmax is increased by 19.28 % and in 32 tap with 16 bit, it increases by 29.74 %. The Low-pass RNS FIR filter is designed for a cut-off frequency of 50 Hz and generated filter coefficients in MATLAB and implemented to denoising the ECG signal.