Design of hardware efficient FIR filter: A review of the state-of-the-art approaches

Abstract

Digital signal processing (DSP) is one of the most powerful technologies which will shape the science, engineering and technology of the twenty-first century. Since 1970, revolutionary changes took place in the broad area of DSP which has made it an essential tool in many engineering applications. Digital filter is considered to be one of the most important components of almost every DSP sub-systems and therefore a number of extensive works had been carried out by researchers on the design of such filter. In order to meet the stringent requirements of filter specification, order of the designed filter is generally assumed to be very large and this leads to high power and area consumption during their implementation. As a matter of fact, design of hardware efficient digital filter has drawn enormous attention which needs to be addressed by various useful means. One popular approach has been to encode the tap coefficients of such filter in the form of sum of signed powers-of-two and thus the operation of multiplication is substituted by simple addition and shifting. This paper presents a detailed review of the basic design approaches applicable for the synthesis of hardware efficient finite duration impulse response (FIR) filter. Both the traditional and heuristic search algorithms have been incorporated and properly arranged in this review.

Keywords

• Common sub-expression elimination (CSE)
• Differential coefficient method (DCM)
• Genetic algorithm (GA)
• Minimal difference differential coefficients method (MDDCM)
• Mixed integer linear programming (MILP)
• Multiple constant multiplication
• Multiplier-less filter
• Pseudo floating point (PFP)