Impact of Memory Hierarchy on Memory Encryption Performance

Abstract

Memory encryption with authentication protects critical applications from attackers with physical access. Memory encryption introduces memory access latency overhead due to the cryptographic computations and metadata accesses in DRAM. We propose using a metadata cache to reduce latency and report the results of an experimental and simulation evaluation of the impact of the DRAM and metadata cache on the overall latency of memory encryption schemes based on Intel SGX and Encryption for Large Memory integrity trees on an FPGA-based platform with DDR3 DRAM. We present the results of an end-to-end performance evaluation of the RISC-V RocketChip soft-core and the memory encryption with several metadata cache configurations.

Keywords

• Authentication tree
• embedded systems
• experimental evaluation
• memory encryption