Design and Implementation of Efficient Multi-branch Predictor

Abstract

Branch prediction is a momentous technology guarantee for processor performance, especially for the widely used superscalar processor. The properties of the branch predictor significantly affect the overall performance, power consumption, and area of the processor. To obtain a more cost-effective branch predictor in the superscalar processor, an attempt is made to use a single TAGE (tagged geometric history length) predictor to predict the branches within the fetch width. The championship branch prediction platform is used to evaluate the performance of the predictor, and its prediction ability is sufficient to meet the prediction conditions. However, in practice, conflicts in both the predictor and branch target buffer affect its performance. To solve the above problem, this paper adds additional prediction paths based on a single TAGE branch predictor and independently saves and predicts additional branch instruction information. This predictor is implemented in the processor using hardware description language and compared with a single TAGE branch predictor to perform standard benchmark programs for embedded processors, dhrystone, coremark and embench. Experimental results show that the performance of the optimized branch predictor is improved by 14.1 percentage points, while the storage overhead is only increased by 9.06%. Finally, through the analysis of the experimental data, it is found that this scheme is not only conducive to the prediction of additional branch instructions, but also can achieve more accurate prediction of single branch instruction through more accurate acquisition of branch history information.

Keywords

• branch prediction; tagged geometric history length (tage); embedded; superscalar; processor