Boosted Spin Channel Networks for Energy-Efficient Inference

Abstract

Computational scaling beyond silicon electronics based on Moore's law requires the adoption of alternate state variables such as electronic spin. Multiple research efforts are underway exploring both Boolean and non-Boolean design space using spin devices in order to make their energy and delay benefits competitive to CMOS. In this paper, we propose spin channel networks (SCN), where the exponential decay property of spin current along the spin channel is exploited to achieve energy-efficient dot product implementation for inference applications. As the use of exponentially decaying spin current for analog computation enforces severe locality constraints, we employ adaptive boosting to design an ensemble of tiny SCNs that work in unison to solve any binary classification task. Such boosted SCNs achieve up to 112× and 14× higher energy efficiency over conventional all-spin-logic-based and 20-nm CMOS designs, respectively.

Keywords

• Analog processing circuits
• beyond-CMOS
• boosting
• machine learning
• pattern analysis
• spin transfer torque