Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With &#x0394;&#x03A3; Quantization Cancellation

Abstract

A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7). While fractional-N phase-locked loops (PLLs) and injection-locking techniques with delta–sigma $(\Delta \Sigma )$ quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order $\Delta \Sigma $ modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.

Keywords

• All-digital phase-locked loop (ADPLL)
• delta–sigma modulator (DSM)
• digital-to-time converter (DTC)
• fractional-N
• integral nonlinearity (INL)
• millimeter-wave (mmWave)