Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors

Abstract

We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb source segments improved the transistor metrics (subthreshold swing (SS) and the on-current performance), due to the formation of a nid-InAsSb segment. The devices display a minimum SS of 26 mV/dec and on-current of $10.2 ~\mu \text{A}/\mu \text{m}$ at $V_{\text {DS}}$ of 300 mV. The performance of devices were improved further by optimizing the doping levels which led to record subthermal current of $1.2 ~\mu \text{A}/\mu \text{m}$ and transconductance of $205 ~\mu \text{S}/\mu \text{m}$ at $V_{\text {DS}}$ of 500 mV.

Keywords

• III-V
• source engineering
• steep-slope
• tunnel field-effect transistors (TFETs)
• vertical nanowires