An Integrated Solution to Improve Performance of In-Memory Data Caching With an Efficient Item Retrieving Mechanism and a Near-Memory Accelerator

Abstract

This paper proposes both software and hardware mechanisms based on the near-memory processing (NMP) accelerator to improve the linked list traversal of the in-memory caching. From a software perspective, we propose a simple but an effective mechanism called ITEM JUMP to reduce the number of traversal on list iteration, and additionally, LSB-first parallel linked list traversal unit, which is an NMP-based hardware accelerator is proposed to improve parallel comparison performance of items. The evaluation result shows LSB-first parallel linked list traversal unit can achieve about 34 times better performance in item comparisons than the case where there is no hardware accelerator, and ITEM JUMP can reduce the number of items retrieved by up to 42%. The proposed NMP-based hardware accelerator also reduces the memory access overhead by 61%–83% compared to a simple parallel linked list traversal unit that simply loads and compares data as fast as possible.

Keywords

• Database system
• accelerator architectures
• memory architecture
• in-memory database
• linked list traversal acceleration
• near memory processing