Parallel Concatenated Block Codes Constructed by Convolutional Interleavers

Abstract

This paper presents the application of convolutional interleavers for constructing high performance parallel concatenated block (PCB) codes. The utilized interleaver is operated as a block interleaver, when the number of stuff bits is applied at the first and end parts of the interleaving. A modification is conducted to reduce the number of stuff bits and ensure that every block of the interleaved data has at least one stuff bit. Conducted simulations confirm that with the similar code length and rate, the newly proposed codes have close or better performance than other well-known codes recommended for the global telecommunications standards.

Keywords

• Parallel concatenated block codes
• convolutional interleavers
• upper bound of probability of error
• cyclic codes
• low-density parity-check (LDPC) codes