Methodology for developing virtual platforms from power-aware to power- and thermal-aware at electronic system level

Abstract

With the growth of complex multiprocessor system-on-chip design and the evolution of process technology, it is crucial to address thermal issues owing to the high-power density of chips. Electronic system level (ESL) design is an acknowledged effective methodology to explore system design by virtual platforms (VPs) at the early stages of integrated circuit (IC) design. Therefore, power- and thermal-aware (PTA) VPs at the ESL are required to explore the thermal issues at the early stages of IC design. Current VPs at the ESL are less discussed in the thermal issues. Therefore, the authors propose a methodology to easily develop VPs from power awareness to power and thermal awareness. In the methodology, a refined thermal engine that has lower computational complexity is proposed to analyse the heat of ICs, and it has high compatibility for integration with power-aware (PA) VPs. In addition, the thermal analysis in the methodology considers the thermal effects of leakage power consumption to reflect the physical temperature of ICs. Thus, system designers can utilise the proposed methodology to easily develop their PA VPs into PTA VPs.

Keywords

• three-dimensional integrated circuits
• thermal analysis
• integrated circuit design
• computational complexity
• system-on-chip
• virtual platforms
• thermal issues
• electronic system level design
• integrated circuit design
• thermal-aware VPs
• IC design
• power awareness
• refined thermal engine
• power-aware VPs
• thermal analysis
• thermal effects
• leakage power consumption
• system designers
• PA VPs
• PTA VPs
• ESL design
• complex multiprocessor system-on-chip design
• power-aware VPs
• computational complexity
• physical temperature