An enhanced approach towards improving the performance of embedding memory management units into Network-on-Chip

Abstract

Network-on-Chip (NoC) initiates the design procedure of interconnection network into SoC - System-on-Chip. The current technique overcomes the drawbacks of traditional bus-based SoC, for instance, poor scalability, small-link bandwidth, and large delay. The network-on-Chip systems required minimum buffering space and low-latency requirements. Here, the FIFO buffer is utilized as a virtual channel to evade deadlock issues and thus enhances throughput. The current research focused on an enhanced toward improving Embedding-Memory-management- Units performance into Network-on-Chip. Here, the 3D NoC was considered in the study for Noc improvement and has achieved high performance. Further, A first-in-first-out (FIFO) buffer was used in NoC routers to store the data packets temporarily. Eventually, the RAM -random access memory was proposed that serves as a link between the crossbar switch and the input ports. The simulation result of the current research results in only 0 to 16 memory for data storage in a stack out of 64, with the almost empty signal being high.

Keywords

• FIFO
• Memory Management Unit (MMU)
• NoC
• Multi processor system
• Distribute MMU
• Centralized MMU