Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator

Abstract

Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number Modelling (SV-RNM) as it’s one of the essential blocks in any Integrated Circuit (IC) and a feedback loop system. It uses the Piece-Wise Linear (PWL) technique to model the loop filter with higher orders, higher than a first-order Low Pass Filter (LPF). The PWL technique needs both the value and the slope information so that the values between the samples can be interpolated, this is represented by the User-Defined Type (UDT) and Net (UDN). A fractional divider is modelled using the Sigma-Delta modulator of the Multi-stAge noiSe sHaping (MASH) 1-1-1 topology to generate the fractional part. Modelling non-linear effect like the phase noise of each sub-block, which is converted to the Root Mean Square (RMS)-jitter, by using the ‘class’ datatype that takes complex variables of real and imaginary values then returns some functionalities on these complex variables. Moreover, taking the loading effect due to capacitances and resistances at the output by using the User-Defined Resolved Nets (UDRN). The simulation results ensure that there is an accuracy improvement in the expected PLL outputs compared to the outputs from the transistor level with a much faster simulation time as an event-driven simulator is used.

Keywords

• Real number modeling (RNM)
• SystemVerilog (SV)
• user-defined types (UDT)
• user-defined resolved nets (UDRN)
• phase locked loops (PLL)
• fractional dividers