Scalable and compact photonic neural chip with low learning-capability-loss

Abstract

Photonic computation has garnered huge attention due to its great potential to accelerate artificial neural network tasks at much higher clock rate to digital electronic alternatives. Especially, reconfigurable photonic processor consisting of Mach–Zehnder interferometer (MZI) mesh is promising for photonic matrix multiplier. It is desired to implement high-radix MZI mesh to boost the computation capability. Conventionally, three cascaded MZI meshes (two universal N × N unitary MZI mesh and one diagonal MZI mesh) are needed to express N × N weight matrix with O(N 2) MZIs requirements, which limits scalability seriously. Here, we propose a photonic matrix architecture using the real-part of one nonuniversal N × N unitary MZI mesh to represent the real-value matrix. In the applications like photonic neural network, it probable reduces the required MZIs to O(Nlog2 N) level while pay low cost on learning capability loss. Experimentally, we implement a 4 × 4 photonic neural chip and benchmark its performance in convolutional neural network for handwriting recognition task. Low learning-capability-loss is observed in our 4 × 4 chip compared to its counterpart based on conventional architecture using O(N 2) MZIs. While regarding the optical loss, chip size, power consumption, encoding error, our architecture exhibits all-round superiority.

Keywords

• neural network
• photonic computation
• silicon photonics