Dianzi Jishu Yingyong (Jan 2019)

Design of input stage amplifier circuit for power operational amplifiers

  • Wang Yongyong,
  • Yang Fashun,
  • Wang Decheng,
  • Hu Rui,
  • Ma Kui

DOI
https://doi.org/10.16157/j.issn.0258-7998.181617
Journal volume & issue
Vol. 45, no. 1
pp. 27 – 30

Abstract

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An input stage amplifier is designed for a power operational amplifier based on 70 V high voltage bipolar technology. The amplifier circuit implements a differential telescopic cascode pair using p-type JFETs. It has figure of merits involving low bias current, low offset voltage and current, and high CMRR. The common-collector common-emitter(CC-CE) configuration is used as the load for the input stage circuit in order to reduce the impact resulting from the load and improve the voltage gain as well. Simulation results based on Spectre simulator indicate that the input stage amplifier circuit has achieved 20 pA input bias current,0.11 mV offset voltage and 0.57 fA offset current,while the voltage gain is 89 dB and the unit gain-bandwidth is 8.13 MHz, with the CC-CE load.

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