Using HLS to Develop FPGA Heterogeneous Acceleration System: Problems, Optimization Methods and Opportunities

Abstract

Currently, field programmable gate arrays (FPGAs) are favored by both academia and industry due to their programmability and excellent energy efficiency ratio. However, traditional FPGA development based on hardware description languages faces programming challenges. Hardware description languages, which are different from commonly used high-level languages, hinder software developers from utilizing FPGAs. High-level synthesis (HLS) enables developers to directly develop FPGA hardware from high-level languages such as C/C++, and is widely regarded as the preferred solution to this problem. In recent years, there have been many works in academia on HLS, dedicated to solving various problems in the HLS application process and improving the performance of systems developed through HLS. This paper lists feasible optimization directions from the perspective of heterogeneous system developers around the issue of developing FPGA heterogeneous systems using HLS. At the compilation optimization level, HLS tools can automatically generate high-performance RTL designs by inserting compilation guidance and designing efficient spatial exploration algorithms. At the memory access optimization level, HLS tools can set up buffers, split and replicate data to improve the overall system bandwidth. At the parallel optimization level, HLS tools can implement statement-level, task-level and board-level parallelism. Meanwhile, some technologies such as DSL, although they cannot directly improve the performance of heterogeneous acceleration systems, can further enhance the usability of HLS tools. Finally, this paper summarizes some challenges currently faced by HLS and prospects the future research on HLS.

Keywords

• field programmable gate array (fpga); high-level synthesis (hls); heterogeneous system; high-level language; compiling optimization