Exploring Multi‐Bit Logic In‐Memory with Memristive HfO2‐Based Ferroelectric Tunnel Junctions

Abstract

Abstract The increasing demand for data movement and energy consumption in physically separate von Neumann architectures, where the processor and memory are distinct entities, highlights the severity of the memory‐wall problem. Thus, memristor‐based logic‐in‐memory (LiM) has garnered significant interest as it is a paradigm that enables both logic and memory functionalities to be performed within a single device. Ferroelectric tunnel junctions (FTJs) have the advantages of low energy consumption and high scalability; thus, they are particularly appropriate for use as analog memristors in LiMs. Precise and accurate programming of the analog resistance states in FTJs is essential to achieve an efficient memristor‐based LiM design. However, existing switching models for FTJs cannot completely consider the ferroelectric domain switching, which challenges multi‐bit LiM operations. This particularly applies in cases involving updates from one intermediate resistance state (IRS) to another IRS, such as transitioning from State 01 to 10 in 2‐bit LiM. In this study, a novel phenomenon associated with domain switching is observed in the IRS of an HZO FTJ device and applied it to an LiM implementation. These findings can contribute to the operational accuracy and update rules of not only FTJ‐based LiMs but also other FTJ applications, such as crossbar arrays.

Keywords

• ferroelectric tunnel junction
• intermediate resistance state
• parallel logic‐in‐memory