IEEE Access (Jan 2024)

iSensMex-POT, a Potentiostat Platform for Human Health Applications

  • Gregorio Zamora-Mejia,
  • Victor H. Carbajal-Gomez,
  • Luis C. Alvarez-Simon,
  • Alejandro Silva-Juarez,
  • Alejandro I. Bautista-Castillo,
  • Sergio A. Rosales-Nunez,
  • Jose M. Rocha-Perez,
  • Francisco Barbosa-Escudero,
  • Margarita Sanchez-Dominguez,
  • Daniel Durini

DOI
https://doi.org/10.1109/ACCESS.2024.3496353
Journal volume & issue
Vol. 12
pp. 169050 – 169068

Abstract

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This work introduces the iSensMEX-POT platform, a potentiostat-based detection system for conducting cyclic voltammetry measurements. It consists of a mixed-mode application-specific integrated circuit (ASIC) and a user digital interface unit based on Raspberry/Python platform. The ASIC consists of three main building blocks: a potentiostat built by three operational amplifiers (OpAmps) working as an analog front-end, a 10-bit R2R digital-to-analog converter (DAC) and a 10-bit successive-approximation analog-to-digital converter (SAR-ADC) composing the mixed signal mode processing stage, and a digital finite state machine using the Inter-Integrated Circuit (I2C) protocol conforming the digital data processing and transmission section. The Raspberry controls the ASIC using the I2C, writes a digital words into the ASIC’s registers to replicate a triangular cyclic voltammetry signal with a scan rate of 200 mV/s over a range of ±1 V, and reads the digitized data from the SAR-ADC. The Raspberry platform displays the resulting waveform on a touch-screen using a graphical user interface (GUI). Also, a precision model based on the open-loop gain of the amplifier and an output noise quantification model were developed and applied to design a highly accurate potentiostat based on three amplifiers. The proposed platform’s functionality and accuracy was validated by comparing the data gathered by the iSensMex-POT with the data obtained with the EVAL-AD5940ELCZ commercial board. The proposed ASIC was mathematically modeled, simulated and fabricated in a 180 nm CMOS standard technology, featuring a silicon area of 1.39 mm2 and a power consumption of 52.99 mW (16.05 mA @ 3.3 V).

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