A low‐voltage and low‐power current‐mode winner‐take‐all (maximum) circuit

Abstract

Abstract In this Letter, a new low‐voltage and low‐power current‐mode winner‐take‐all (WTA) circuit is proposed. The proposed circuit is able to operate with a low supply voltage requirement while exhibiting a high accuracy. Moreover, the sensitivity of the circuit to the process variations and mismatches is improved. The proposed WTA circuit is designed and simulated in a 65‐nm technology with a supply voltage of VDD = 0.9 V. The post‐layout simulation results show that the power consumption of the proposed circuit is about 72 μW with the input dynamic range of 40 μA.

Keywords

• analogue integrated circuits
• comparators (circuits)
• integrated circuit design