Consideration of parasitic effects on buses during early IC design stages

Abstract

Complex integrated systems contain more and more on-chip components which exchange data and access memories via buses. To consider parasitic effects on bus structures during the early design phase appropriate models and wiring methods must be available. A RC-Pi model is proposed to model the load of a bus driver cell that also considers capacitive coupling between the signal lines. On the basis of simple estimations it is shown under what conditions the influence of inductance on the bus is negligible. Furthermore a method to consider inductive effects is shown. An early consideration of parasitic effects on global interconnect structures and an assertion which effects have to be considered is mandatory to effectively estimate the behavior of wires. Hence it also helps to avoid wrong assumptions.