Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning

Abstract

Accurate current-voltage (I-V) modeling based on the Berkeley short-channel insulated-gate field-effect transistor model (BSIM) is pivotal for integrated circuit simulation. However, the current BSIM model does not support a buried-channel-array transistor (BCAT), which is the structure of the state-of-the-art commercial dynamic random access memory (DRAM) cell transistor. In this work, we propose an intelligent I-V modeling technique that combines genetic algorithm (GA) and deep learning (DL). This hybrid technique facilitates both optimization of BSIM parameter and accurate I-V modeling, even for devices not originally supported by BSIM. Additionally, we extended application of the DL to model one of the principal degradation mechanisms of transistor, the hot-carrier degradation (HCD). The successful modeling results of I-V characteristic and device degradation demonstrated that devices not supported by BSIM can be accurately modeled for integrated circuit simulations.

Keywords

• BSIM-CMG
• deep learning
• genetic algorithm
• I-V modeling
• compact modeling
• BCAT