Optimization and FPGA implementation of RS coding algorithm

Abstract

Aiming at the problems of large amount of computation and high complexity of multiplication of Galois Field(GF) in the common RS coding algorithm, the RS coding module is optimized and the multiplier factor is obtained. The module completes the calculation of the RS code multiplier factor, reduces the complexity of the Galois field multiplication operation in the FPGA implementation process, and reduces the amount of computation. The test results show that the optimized RS-coded FPGA is simple and effective, and the coding is accurate. The coding result is consistent with the theoretical results obtained by MATLAB. It can be applied to RS coding of arbitrary code length, and complex multi-factor communication in mobile communication and space communication.

Keywords

• rs coding
• galois field
• algorithm optimization
• fpga