IEEE Access (Jan 2024)

Switching Activity Reduction of SOP Networks

  • Marcin Kubica,
  • Boleslaw Pochopien,
  • Dariusz Kania

DOI
https://doi.org/10.1109/ACCESS.2024.3442975
Journal volume & issue
Vol. 12
pp. 112984 – 112994

Abstract

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An extremely important aspect of the synthesis of digital circuits is obtaining solutions optimized in terms of energy consumption. This can be achieved by limiting the dynamic power, depending on the switching activity of the nodes of the implemented logic network. The article proposes a new technology mapping method leading to a reduction in switching activity. An approach known from the literature using an output graph was improved, the essence of which lies in the analysis of the created model of the switching system. The essence of this improvement was to take into account additional parameters related to switching the gateway network. The main contribution of the article is the use of a switching model in the form of an innovative switching graph to limit the number of switches of the logic network. The presented approach is focused on the sum-of-products (SOP) architecture. The reason for this choice is that it is the most elementary and universal form of mapping a combinational function, often implemented in some families of programmable devices. The proposed approach resulted in a significant reduction in switching activity compared to the classical implementation, by 68.9%, 70.6% and 70.2%, respectively, for SOP architectures with 3, 5 and 7 input sums. Of the 20 test systems considered, no significant improvement in switching activity was achieved compared to the classical method, only for 2, 3 and 4 cases, respectively, for SOP architectures with 3, 5 and 7 input sums. The results presented in the article confirm the effectiveness of the proposed methods.

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