Design of high-definition video acquisition system based on FPGA

Abstract

With the rapid development of multimedia display and transmission technology, a full HD(resolution 1 920×1 080) video acquisition and display system based on HDMI interface is designed. The system uses 5 million pixel level CMOS camera OV5640 as front-end data source, and can gather full HD video signal, and uses Xilinx spartan6 series FPGA as control chip. In order to solve the drag-down phenomenon caused by the shortage of high speed and large capacity video data cache capacity and speed, the system adopts a piece of DDR3 SDRAM with 4 Gbit capacity of Micron company as buffer medium, and combines ping-pong operation. It can solve the cache problem of high speed and large capacity data. In this system, SIL9134 of Silion Image Company is chosen as the HDMI interface chip, which can effectively support the output of full HD video signal. The system can be applied to the fields of military monitoring system , civil multimedia system and medicine.

Keywords

• hdmi
• fpga
• smear phenomenon
• ddr3
• full hd