A Gate Bias and Temperature Dependencies of Contact Resistances in Amorphous Oxide Semiconductor Thin-Film Transistors

Abstract

In this paper, we discuss a gate bias and temperature dependencies of contact resistances in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) while developing a respective model for it. Here, it is found that the contact resistance is a function of the gate bias following a power law. In this power-law function, the scaling factor and exponent have temperature dependencies based on their Arrhenius relations, respectively. These are retrieved from experimental results of bias and temperature-dependent electrical characteristics of the fabricated In-Ga-Zn-O TFTs with two channel lengths, such as transfer characteristics measured for different temperatures. Since the contact resistance as a dominant parasitic-element plays an important role in the AOS TFT operation, the presented model could be a key for an accurate compact TFT model where a gate bias and temperature dependencies are essential.

Keywords

• Amorphous oxide semiconductor
• thin film transistor
• contact resistance
• bias and temperature dependencies
• parasitic element
• compact transistor model