IET Circuits, Devices and Systems (Sep 2021)

Fast OMP algorithm and its FPGA implementation for compressed sensing‐based sparse signal acquisition systems

  • Shirshendu Roy,
  • Debiprasad P. Acharya,
  • Ajit K. Sahoo

DOI
https://doi.org/10.1049/cds2.12047
Journal volume & issue
Vol. 15, no. 6
pp. 511 – 521

Abstract

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Abstract Compressed sensing‐based radio frequency signal acquisition systems call for higher reconstruction speed and low dynamic power. In this study, a novel low power fast orthogonal matching pursuit (LPF‐OMP) algorithm is proposed for faster reconstruction of sparse signals from their compressively sensed samples and the reconstruction circuit consumes very low dynamic power. The searching time to find the best column is reduced by reducing the number of columns to be searched in successive iterations. A novel architecture of the proposed LPF‐OMP algorithm is also presented here. The proposed architecture is implemented on field programmable gate array for demonstrating the performance enhancement. Computation of pseudoinverse in OMP is avoided to save time and storage requirement to store the pseudoinverse matrix. The proposed design incorporates a novel strategy to stop the algorithm without consuming any extra circuitry. A case study is carried out to reconstruct the RADAR test pulses. The design is implemented for K = 256, N = 1024 using XILINX Virtex6 device and supports maximum of K/4 iterations. The proposed design is faster, hardware efficient and consumes very less dynamic power than the previous implementations of OMP. In addition, the proposed implementation proves to be efficient in reconstructing low sparse signals.

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