Design of high reliability and high speed programmable asynchronous FIFO

Abstract

Based on the research of a domestic field programmable gate array(FPGA) chip, an asynchronous first input first output(FIFO) circuit structure with high reliability, high speed and programmability is proposed. By adding the full/empty warning threshold and the full/empty state bit, the programmability of the proposed asynchronous FIFO is improved. Meanwhile, the reliability of the circuit is improved by using the Gray code pointer for comparation. On this basis, a new criterion for judging the full/empty state is proposed, which is applied to further improve the system working speed and logic utilization. Based on the United Microelectronics Corporation(UMC) 28 nm standard complementary metal oxide semiconductor(CMOS) process, the circuit design is carried out by fully customized method. The simulation results show that the proposed asynchronous FIFO has a maximum operating frequency of 666.6 MHz and an average power consumption of 7.1 mW at 1 V standard voltage.

Keywords

• programmability
• asynchronous fifo
• full/empty warning threshold
• gray code pointer
• full/empty judgment