Design and implementation of PCIe on UM-BUS test system

Abstract

The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1.1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this paper realizes the application scheme of PCIe1.1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s, which satisfies the bandwidth requirements of the UM-BUS bus test system.

Keywords

• UM-BUS
• bus test system
• PCIe bus
• BMD
• data communication