Discover Nano (Jul 2024)
Nanosheet integration of induced tunnel field-effect transistor with lower cost and lower power
Abstract
Abstract Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet structure with a vertically stacked design, featuring a high I ON/I OFF ratio. This Nanosheet design is combined with an induced tunnel field-effect transistor. By utilizing SiGe with a carrier mobility three times that of Si and employing a line tunneling mechanism, the research successfully achieves superior Band to Band characteristics, resulting in improved switching behavior and a lower Subthreshold Swing (SS). Comparative studies were conducted on three TFET types: Nanosheet PIN TFET, Nanosheet Schottky iTFET, and Fin iTFET. Results show that the Nanosheet PIN TFET has a higher I ON/I OFF ratio but poorer SSavg values at 47.63 mV/dec compared to the others. However, with a SiGe Body thickness of 3 nm, both Nanosheet iTFET and Fin iTFET exhibit higher I ON/I OFF ratios and superior SSavg values at 17.64 mV/dec. These findings suggest the potential of Nanosheet iTFET and Fin iTFET for low-power, lower thermal budgets, and fast-switching applications.
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