Trusted and controlled design route complex-functional VLSI using foreign and domestic CAD systems

Abstract

The article discusses the design flow for complex functional VLSI circuits at the stage of synthesis and physical synthesis using foreign and domestic CAD systems, which makes it possible to ensure, on the one hand, the characteristics of the VLSI in accordance with the capabilities of foreign CAD systems, on the other hand, to exclude undeclared functions that are possible due to use of Western CAD systems. The design flow is divided into two main stages: logical synthesis and physical synthesis. Security is ensured by using only domestic trusted RTL codes and IP blocks and checking, carried out by domestic trusted CAD, for compliance of the source RTL code obtained as a result of design on foreign CAD with the netlist, as well as analysis for the absence of circuits and circuits not connected to inputs/outputs the developed scheme. In addition to domestic CAD, it is possible to use verified CAD based on the freely available YOSYS. The design flow should include four additional domestic ERC checks; the functions of these checks are given. The design flow is intended for the creation of complex functional VLSI by Russian design centers and Centers for collective design of radio-electronic products. The flow of synthesis and physical synthesis is considered, indicating the names of the files obtained at each stage. A table is presented of the CAD products used by Synopsys, Cadence, Mentor Graphics (Siemens) for carrying out the considered design stages with technological standards of 28-65 nm. In conclusion, a justification for the design flow for complex functional VLSI using Western and domestic CAD systems is given and the work necessary for the development of this direction is listed.

Keywords

• design flow, trusted vlsi, synthesis, physical synthesis, vlsi, undeclared functions.