Joint Error Estimation and Calibration Method of Memory Nonlinear Mismatch for a Four-Channel 16-Bit TIADC System

Abstract

Memory nonlinear error greatly reduces the performance of analog-to-digital converters (ADCs), and this effect is more serious in a time-interleaved analog-to-digital converter (TIADC) system. In this study, the sinusoidal wave fitting method was adopted and a joint error estimation method was proposed to address the memory nonlinear mismatch problem of the current TIADC system. This method divides the nonlinear error estimation method into two steps: the nonlinear mismatch error is coarsely estimated offline using the least squares (LS) method, and then accurately estimated online using the recursive least squares (RLS) method. After the estimation, digital post-compensation method is adopted. The obtained error parameters are used to reconstruct the error and then the reconstructed error is reduced at the output. This study used a four-channel 16-bit TIADC system with an effective number of bits (ENOB) value of 10.06 bits after the introduction of a memory nonlinearity error, which was increased to 15.42 bits after calibration by the joint error estimation method. As a result, the spurious-free dynamic range (SFDR) increased by 36.22 dB. This error estimation method can improve the error estimation accuracy and reduce the hardware complexity of implementing the error estimation system using a field programmable gate array (FPGA).

Keywords

• time-interleaved analog-to-digital converter (TIADC)
• memory nonlinear effect
• joint estimation
• Volterra series
• mismatch error