Hardware Reduction for FSMs With Extended State Codes

Abstract

A method is proposed for reducing chip area occupied by logic circuits of FPGA-based Mealy finite state machines (FSMs). The proposed method aims at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. The proposed method combines positive features of such state assignment methods as extended (ESCs) and composite (CSCs) state codes. The method is based on finding a partition of the set of internal states by classes of compatible states. To reduce LUT count, we propose a special kind of states codes named mixed state codes. These codes include two parts. The first part includes the maximum binary codes of states as elements of some partition class. The second part consists of the code of corresponding partition class. Unlike CSCs, the proposed approach allows obtaining partial state codes having different lengths. Unlike ESCs, all partial state codes consist of the same variables. Using mixed state codes allows obtaining LUT-based FSM circuits with exactly two levels of logic. The first level generates partial Boolean functions. The second level combines them into FSM outputs and input memory functions. If some conditions hold, then both levels consist of single-LUT circuits. Example of FSM synthesis based on mixed state codes is shown. The conducted experiments prove that the proposed approach allows reducing hardware compared with FSMs based on JEDI, one-hot state codes, CSCs and ESCs. On average, the proposed method reduces the value of LUT count by 6.21% compared to CSC-based FSMs and 22.21% compared to ESC-based counterparts. The advantages of the proposed approach grow with the growth of FSM complexness. An additional positive effect of the proposed method is a slight increase in the operating frequency.

Keywords

• Mealy FSM
• FPGA
• LUT count
• synthesis
• extended state codes
• composite state codes