Wafer-Level Vacuum-Packaged Electric Field Microsensor: Structure Design, Theoretical Model, Microfabrication, and Characterization

Abstract

This paper proposes a novel wafer-level vacuum packaged electric field microsensor (EFM) featuring a high quality factor, low driving voltage, low noise, and low power consumption. The silicon-on-insulator (SOI) conductive handle layer was innovatively used as the sensing channel to transmit the external electric field to the surface of the sensitive structure, and the vacuum packaging was realized through anodic bonding between the SOI and glass-on-silicon (GOS). The fabrication process was designed and successfully realized, featured with a simplified process and highly efficient batch manufacturing, and the final chip size was only 5 × 5 mm. A theoretical model for the packaged device was set up. The influence of key parameters in the packaging structure on the output characteristics of the microsensor was analyzed on the basis of the proposed model. Experiments were conducted on the wafer-level vacuum-packaged EFM to characterize its performance. Experimental results show that, under the condition of applying 5 V DC driving voltage, the required AC driving voltage of the sensor was only 0.05 VP, and the feedthrough was only 4.2 mV. The quality factor was higher than 5000 and was maintained with no drop in the 50-day test. The vacuum in the chamber of the sensor was about 10 Pa. A sensitivity of 0.16 mV/(kV/m) was achieved within the electrostatic field range of 0–50 kV/m. The linearity of the microsensor was 1.62%, and the uncertainty was 4.42%.

Keywords

• wafer-level vacuum packaging
• electric field microsensor
• MEMS
• structural capacitance model