S²RAM: Optimization of SRAM With Memory Access Patterns

Abstract

This paper presents a static sequential-random-access memory (S2RAM) designed to enable low-power and high-performance operations for workloads involving sequential memory accesses. Considering the address configuration and internal operation of column-interleaved SRAM, we propose an optimized memory structure and peripheral circuitry that can exploit access patterns as opportunities for low-cost operation. In the proposed S2RAM, word-line (WL) activation is restricted by using bit-line (BL) as temporary storage in case of memory access in which only column addresses are sequentially changed. In order to prevent the BL leakage-induced data corruption, a BL clamper is also proposed. The optimized design method of the controller and assist scheme for using reconfigurable access modes in the proposed S2RAM is also presented. The proposed 16Kb S2RAM macro has been implemented using a 28nm CMOS technology. Numerical results show that the proposed S2RAM saves up to 76% of operating energy compared to conventional SRAM at the cost of 8% increased area.

Keywords

• SRAM
• low-power
• clamper
• leakage
• assist
• burst operation