An ultra-low power QCA based vedic multiplier for digital radar application

Abstract

Quantum-dot cellular automata (QCA) is a promising nanotechnology that appears to meet the requirements of high speed radar applications. Due to its advantages, including its extremely low power dissipation and less occupied area, it is highly regarded. The multiplier module is an essential component in Phased Array Radar (PAR). In the real-time PAR based systems, many applications like digital beam forming, local oscillators, and communication receivers etc. requires multiplication operation. However, the most important factors in these systems are the area and power consumption. This paper presents an ultra-low power vedic multiplier using QCA technology, and it provides the effective clocking, reduce the number of cells, and low energy dissipation. The 4×4 vedic multiplier utilizes only 2940 cells and occupies 7.33μm2 area with 7.64×10−1eV of energy dissipation. The total consumed power of this module is 1.61nW. This architecture outperforms complementary metal-oxide-semiconductor (CMOS) based circuits in terms of power by 90%. The proposed contribution will initiate a new direction of research into real-time PAR based systems.

Keywords

• Vedic multiplier
• Binary full adder
• Power consumption
• Energy dissipation
• QCA