Zhejiang Daxue xuebao. Lixue ban (Sep 2001)

Hardware mechanism for redundancy restraint and the analysis of their working procedure(冗余抑制的硬件实现及作用过程分析)

WUXun-wei(吴训威),
LUYang-jian(卢仰坚)

Affiliations

WUXun-wei(吴训威): 1.Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China( 1.宁波大学电路与系统研究所，浙江　宁波　315211)
LUYang-jian(卢仰坚): 2.Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China( 2.浙江大学信息与电子工程学系，浙江　杭州　310027)

DOI
Journal volume & issue: Vol. 28, no. 5
pp. 498 – 506

Abstract

基于低功耗设计的要求，本文对数字系统中冗余现象的普遍性进行分析，研究了实施冗余抑制功能的各种基本结构，并进行了抑制作用的时间分析，这些均为在电路的低功耗设计中有效地应用冗余抑制技术提供了研究基础.

Published in Zhejiang Daxue xuebao. Lixue ban

ISSN: 1008-9497 (Print)
Publisher: Zhejiang University Press
Country of publisher: China
LCC subjects: Science: Mathematics: Instruments and machines: Electronic computers. Computer science; Science: Physics
Website: https://www.zjujournals.com/sci/EN/1008-9497/home.shtml

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