Design of K-Band CMOS Extended Cascode Power Amplifier With Second Harmonic Termination to Enhance Output Power

Abstract

In this study, an extended cascode structure is proposed to enhance the output power of a K-band CMOS power amplifier. The extended cascode structure can increase supply voltage by additionally stacking a common-gate (CG) transistor in the typical cascode structure, thereby ensuring high output power. In order to optimize the operation of the extended cascode structure, the admittances of the internal nodes of the structure were analyzed. Based on the theoretical values of the analyzed admittances, the initial value of the design parameter of the output matching network was obtained, and then the tuning process was performed. Capacitive neutralization, second harmonic termination, and RC-feedback techniques were applied to the designed power amplifier to ensure stability, linearity, and output matching, respectively. In order to verify the feasibility of the proposed structure, a 21.5 GHz power amplifier was designed using the 65-nm RFCMOS process. The measured saturation power, P1dB, gain, and maximum power-added efficiency (PAE) measured at 21.5 GHz of the designed power amplifier were 24.2 dBm, 21.4 dBm, 28.4 dB and 25%, respectively. When measured using a 21.5 GHz 64-QAM modulated signal with a 100 MHz bandwidth, the measured average output power satisfying 5.62% of EVM was 14.7 dBm.

Keywords

• Cascode structure
• CMOS
• neutralization technique
• power amplifier
• stability
• stacked-FET structure